1. Field of the Invention
The present invention relates to a technology of removing nanotopography produced on a surface of a semiconductor wafer in a process of semiconductor fabrication.
2. Description of the Related Art
Nanotopography refers to nanometer scale height variation or unevenness, produced on a surface of a semiconductor wafer, a spatial wavelength thereof falls in a range of about 0.2 mm through 20 mm and a difference of height between wave top and wave bottom (hereinafter, referred to as wave height) falls in a range of 1 through several hundreds nm.
There has been adopted multilayer wiring technology in a semiconductor device and to meet request of the wiring technology, there has been developed a chemical and mechanical composite polishing process referred to as CMP (Chemo-Mechanical Polishing). Although the surface of a semiconductor wafer can always be planarized highly accurately by the CMP technology, there poses a problem by very fine unevenness having different levels, so-to-speak nanotopography which cannot be removed even by the CMP apparatus. This is a problem which attracts attention since yield of a semiconductor device is deteriorated because there is caused film thickness nonuniformity in an insulating layer film on the surface of a semiconductor wafer.
Nanotopography is said to be cause by all the steps of semiconductor silicon wafer fabrication, for example, doping nonuniformity in a step of pulling silicon crystal, lapping mark, polishing mark, slicing mark, etching mark or the like and among them, particularly, etching mark (removal of damage of bottom face) is said to constitute maximum cause.
In order to restrain nanotopography based on various causes in this way from producing, a wafer maker carries out various devises such as fine caution on respective processes, shift to a process which is difficult to produce nanotopography (for example, from acidic etching to alkaline etching), or use of a both face mirror wafer and so on. Further, it is the actual situation that a semiconductor wafer producing nanotopography even thereby, is dealt with by using the semiconductor wafer as a semiconductor device at a level at which the produced nanotopography is not problematic, or disposed as a failed product.
Presence of nanotopography is found after a semiconductor silicon wafer has been processed by a number of steps in steps of semiconductor silicon wafer fabrication and therefore, when the presence is found, not only the number of steps and expense which have been paid until the presence is found, are wasted but also an increase in yield of products to a constant level or higher and accordingly, a reduction in fabrication cost, are made difficult. Therefore, it is mostly desired to develop a technology of preventing nanotopography from producing basically, besides the development, it is necessary to pay a consideration to how to effectively remove nanotopography which has already been produced.
Plasma etching apparatus is known as an apparatus for planarizing a silicon wafer having very small unevenness on its surface. According to the apparatus, sulfur hexafluoride (SF6) gas or the like is formed into plasma at inside of a plasma generating apparatus and F activated species formed by the plasma formation is injected from a nozzle and is blown to the surface of a silicon wafer. The nozzle is scanned at speed in accordance with unevenness of the surface of the silicon wafer and by controlling scanning speed, much of material at projected portions is removed to thereby carry out planarizing.
In this case, the step referred to as planarizing actually signifies uniform formation of a thickness of a silicon wafer and very small unevenness referred to as planarized, is provided with a period equal to or larger than 10 mm and a height (wave height) of 100 through several hundreds nm (nanometer). Therefore, a degree of the planarizing differs from unevenness of the above-described nanotopography (wavelength: 0.2 mm through 20 mm, wave height: 1 through several hundreds nm) in view of the level and accordingly, nanotopography cannot be machined by using an existing plasma etching apparatus for planarizing machining.
As described above, it is a problem of the invention to provide a technology for removing nanotopography which has already been produced on a surface of a semiconductor wafer.